FIGS. 3(a) to 3(g) show a prior art production method for a HBT (hetero bipolar transistor).
In FIG. 3(a), reference numeral 1 designates a semi-insulating GaAs substrate. An n.sup.+ type GaAs layer 2 constituting a sub-collector layer having a thickness of about 5000 angstroms and impurity concentration of 5.times.10.sup.18 cm.sup.-3 is disposed on the substrate 1. An n type GaAs layer 3 constituting a collector layer having a thickness of about 5000 angstroms and impurity concentration of about 5.times.10.sup.16 cm.sup.-3 is disposed on the n.sup.+ type GaAs layer 2. A p.sup.+ type GaAs layer 4 constituting a base layer having a thickness of about 1000 angstroms and impurity concentration of about 1.times.10.sup.19 cm.sup.-3 is disposed on the n type GaAs layer 3. Reference numeral 5a designates a grading layer between the p type GaAs layer 4 and an emitter layer 5, comprising n type Al.sub.x Ga.sub.1-x As layer where x gradually varies from 0 to 0.3 in the direction of emitter layer 5 having a thickness of about 500 angstroms and impurity concentration of about 3.times.10.sup.17 cm.sup.-3. An n type Al.sub.0.3 Ga.sub.0.7 As layer 5 constituting an emitter layer having a thickness of about 1000 angstroms and impurity concentration of about 3.times.10.sup.17 cm.sup.-3 is disposed on the grading layer 5a. Reference numeral 5b designates a grading layer between the emitter layer 5 and an emitter cap layer 6, comprising n type Al.sub.x Ga.sub.1-x As layer where x gradually varies from 0.3 to 0 in the direction of cap layer 6 having a thickness of about 500 angstroms and impurity concentration of about 3.times.10.sup.17 cm.sup.-3. An emitter cap layer 6 comprising n.sup.+ type GaAs having a thickness of about 2000 angstroms and impurity concentration of about 5.times.10.sup.18 cm.sup.-3 is disposed on the grading layer 5b.
In FIG. 3(b), reference numeral 7 designates an emitter electrode dummy pattern of a first insulating comprising SiON or SiN and having a film thickness of about 5000 angstroms. A p type external base region 8 is produced by ion implantation of Mg.sup.+ ions to a depth of about 3000 angstroms and impurity concentration of about 5.times.10.sup.18 cm.sup.-3.
In FIG. 3(c), reference numeral 9 designates a second insulating comprising SiO and having a film thickness of about 3000 angstroms. Reference numeral 10 designates an insulating region produced by ion implantation of B.sup.+ ions or H.sup.+ ions and having a depth of about 11000 angstroms.
In FIG. 3(d), reference numeral 11 designates a side wall which is produced by reactive ion etching (RIE) of the second insulating film 9.
In FIGS. 3(e) and 3(f), reference numeral 12 designates a base electrode resist pattern, and reference numerals 13 and 13a designate base electrode metal such as AuZn.
In FIG. 3(g), reference numeral 14 designates a first or second insulating film which is flattened using photoresist and uniform speed etching of the photoresist and the insulating film by RIE. Reference numeral 15 designates an emitter electrode such as a AuGe alloy.
The production process will be described.
The structure shown in FIG. 3(a) is produced by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD).
Next, as shown in FIG. 3(b), a first insulating film comprising SiON or SiN is deposited on the entire surface of the structure shown in FIG. 3(a), and the insulating film is patterned by photolithography to produce a dummy pattern for emitter electrode 7. Then, the n.sup.+ GaAs layer (emitter cap layer) 6 is etched by wet etching using a solution of sulfuric acid, hydrogen peroxide, and water using the dummy pattern 7 as a mask.
Next, Mg.sup.+ ions are ion implanted using the first insulating film 7 as a mask, and an external base region 8 having a depth of about 3000 angstroms and impurity concentration of about 5.times.10.sup.18 cm.sup.-3 is produced.
In FIG. 3(c), the second insulating film 9 comprising SiO is deposited on the entire surface of wafer, and thereafter, B.sup.+ or H.sup.+ ions are ion implanted using a photoresist pattern as a mask. An insulating region 10 having a depth of about 11000 angstroms is produced.
As shown in FIG. 3(d), the second insulating film 9 comprising SiO is etched by RIE using a mixture of C.sub.2 F.sub.6 +CHF.sub.3 +O.sub.2 +He, whereby a side wall 11 is produced. When the second insulating film comprises SiN, the mixture of CHF.sub.3 +O.sub.2 is used. Herein, the etching is conducted under conditions chosen 50 that the first insulating film 7 is not etched (conditions such as substrate temperature and mixing ratio of gas).
As shown in FIG. 3(e), a photoresist pattern 12 is deposited and a metal 13 such as AuZn is vapor deposited on the entire surface. Base electrodes 13a are produced using the photoresist pattern 12 and the first kind of insulating film 7 as a mask, separated from the emitter cap layer 6 with intervals corresponding to the thickness of the side wall 11.
As shown in FIG. 3(f), the photoresist pattern 12, the first insulating film 7, and the side wall 11 are removed by etching with hydrofluoric acid, and unrequired portions of metal 13 is also removed at the same time. Herein, reference numeral 40 designates a collector electrode.
As shown in FIG. 3(g), a first or second insulating film 14 is deposited on the entire surface, and a photoresist is deposited thereon to make the surface flat. Thereafter, equal speed etching of the photoresist and the insulating film 14 by RIE exposes the head portion of the emitter cap layer 6, thereby flattening the insulating film 14.
An emitter electrode metal 15 comprising a AuGe alloy is deposited on the exposed portion of the emitter cap layer 6.
In the prior art production method of an HBT, ion implantation of Mg.sup.+ ions is utilized to connect the base region to the surface and to produce a base electrode at the surface of the device.
In this ion implantation method, however, the impurity concentration of the external base region 8 is low, about 5.times.10.sup.18 cm.sup.-3 at the most, and it is impossible to reduce the external base resistance significantly.
While producing an emitter electrode, the surface flattening using photoresist and the exposure of the emitter cap layer utilizing the equal speed etching of the photoresist and insulating film by RIE exploit the step difference due to the emitter cap layer 6, and the reproducibility and uniformity of the process and product are poor.
The emitter cap layer 6 is an n.sup.+ GaAs layer and is required to have a step of about 2000 to 3000 angstroms. Further, this step is produced by wet etching. Therefore, the reproducibility and uniformity of the emitter width are poor due to the variations in the wet etching and, therefore, precision patterning of the emitter width is difficult.
When the base electrode 13a is spaced from the emitter at intervals equal to the thickness of the side wall, the spacing between the base electrode metal 13 and the emitter electrode dummy pattern 7 is difficult to control. This results in reductions in yield.